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| RDC(R) R2021 RISC DSP Communication FAST ETHERNET RISC PROCESSOR FAST ETHERNET RISC PROCESSOR R2021 Brief Sheet Specifications subject to change without notice, contact your sales representatives for the most update information. Page 1 of 4 REV 1.0 Sep. 20 2006 RDC(R) 1. Features l l CPU Core R2021 RISC DSP Communication FAST ETHERNET RISC PROCESSOR l l - Two Independent DMA Channels Fast Ethernet MAC Ports 2-Port Fast Ethernet MAC with MII interface The MAC packet buffer is cacheble with snooping function RDC's proprietary RISC architecture Five-stage pipeline Operation frequency: 125 MHz Supports an 8K-byte Uniform cache Supports CPU ID Supports 40 PIO pins Bus Interface Supports non-multiplexed address bus A[21:0] With 8-bit or 16-bit Boot ROM bus size 8-bit or 16-bit external bus dynamic access Supports an independent data/address bus for external I/O device l - Interrupt Controller The Interrupt controller with five maskable external interrupts and one non-maskable external interrupt l - Programmable Chip-select Logic Programmable chip-select logic for Memory or I/O bus cycle decoder l - PCMCIA Bus Interface Supports a glueless and simplified 16-bit PCMCIA bus interface l l - Programmable wait-state generator Counter/Timers Three independent 16-bit timers and one independent programmable watchdog timer l ROM/RAM/SDRAM Controller and Addressing Space Supports 16-bit data bus [15:0] 16M-byte memory address space Address[23:0] SDRAM control Interface 64K-byte I/O space Compatible UART Channels Supports two compatible UART serial channels with 16-byte FIFO and hardware flow-control l l l - Operating Voltage Range Core voltage: 2.5V 5% I/O voltage: 3.3V 10% Package Type 128-pin PQFP Specifications subject to change without notice, contact your sales representatives for the most update information. Page 2 of 4 REV 1.0 Sep. 20 2006 RDC(R) R2021 RISC DSP Communication FAST ETHERNET RISC PROCESSOR 2. Block Diagram INT2 INT1 CLKOUTA INT3 INT6-INT5 INT0 NMI DRQ0 DRQ1 X1 VCC GND X2 Clock and Power Management Interrupt Control Unit Timer Control Unit DMA Unit RST_n MAC1 MII 1 Cache MCS_n UCS_n PCS6_n PCS[3:2]_n PCS0_n Chip Select Unit Instruction Queue (64bits) MAC0 MII 0 Micro ROM Control Signal Register File ARDY Refresh Control Unit General, Segment, Eflag Register PIO Unit EA / LA Address 16550 UART Serial Port0 PIO[39:0] Instruction Decoder SD_CLK WE_n CAS_n RAS_n BA[1:0] SDRAM/Bus Interface Unit ALU (Special, Logic, Adder, BSF) Execution Unit 16550 UART Serial Port1 DCD0_n SIN0 DSR0_n CTS0_n RI0_n RTS0_n SOUT0 DTR0_n DCD1_n SIN1 DSR1_n CTS1_n RI1_n RTS1_n SOUT1 DTR1_n A[21:0] D[15:0] BHE_n RD_n ALE WR_n/BWSEL Specifications subject to change without notice, contact your sales representatives for the most update information. Page 3 of 4 REV 1.0 Sep. 20 2006 RDC(R) 3. R2021 RISC DSP Communication FAST ETHERNET RISC PROCESSOR Package Information PQFP 128 pins 23.2 0.2mm 20.0 0.1mm 102 65 103 64 RDC R1610 XXXX-C-QF XX-XXXXX 128 17.2 0.2mm 14.0 0.1mm 39 Pin 1 Identifier 1 38 0.22 0.05mm 0.5mm BSC 3.40mm (Max.) 2.85 0.12mm 0.145 0.055mm 0.25mm (Min.) Seating Plane Specifications subject to change without notice, contact your sales representatives for the most update information. Page 4 of 4 REV 1.0 Sep. 20 2006 |
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